The technology described in this disclosure relates generally to semiconductor devices and more particularly to fabrication of semiconductor devices.
As feature sizes of semiconductor devices continue to shrink, various problems, such as short-channel effects and poor sub-threshold characteristics, often become severe in traditional planar devices. Novel device geometries with enhanced performance, such as FinFETs, have been explored to push toward higher packing densities in devices and circuits. FinFETs usually include semiconductor fin structures formed vertically on a substrate. One or more gate structures are formed over and along the sides of the fin structures to produce faster, more reliable and better-controlled transistors.